University of Wisconsin-Madison College of Engineering Annual Report 2003
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Electrical and Computer Engineering

Nanoscale device

Nanoscale device reveals behavior
of individual electrons

While engineers have a great grasp of how to control electrical charge in circuits, getting rid of heat is another matter. What's missing is a fundamental understanding of how individual electrons generate heat. A new device developed by Associate Professor Robert Blick not only promises to change that, but also will provide insights into harnessing quantum forces for communication and computing.

Robert Blick

Blick, his graduate student Eva Hoehberger and colleague Werner Wegscheider developed a tunable artificial atom for bouncing around individual electrons. The device is just 100 nanometers wide or about one ten-millionth of an inch and will allow researchers to study for the first time, in detail, the influence of heat dissipation on single electron transport in these transistors.

Understanding energy transfer at these levels offers very practical, near-term benefits for chip manufacturers. Lessons learned from the tool could allow engineers to optimize existing technology currently limited by heat dissipation.

In the longer term, the tool could reveal secrets that allow researchers to exploit the power of quantum com-puting and communication. A quantum computer deals with the quantum mechanics of electrons, which can be used to define so-called quantum bits or qubits. These qubits can exist in more than one state simultaneously allowing all possible solutions to a complex problem to be found at once. Key to developing a practical quantum computer is understanding exactly what represents information in such a system and how to get it out of the device. Blick's tool will allow researchers to study information processing on just such a scale.

Fine tuning: Researchers create path to wireless system on a chip

The need for capacity and portability in wireless communications continues to grow as more and more complex integrated chips are designed to exchange information. Future wireless systems will require faster transmission rates, higher operating frequencies to accommodate more channels and users, more functionality, less weight, low power consumption and low cost. Ultimately what's needed is a complete wireless system on a chip. Among all the components in a wireless system, a fully integrated high-frequency and efficiency power amplifier is the most difficult to realize.

Assistant Professor Zhenqiang (Jack) Ma and his team have a solution — higher power Si-based heterojunction bipolar transistors (HBTs). The novel high-frequency silicon-germanium (SiGe) devices make possible a completely on-chip integrated wireless transmitter which, with further integration, paves the way to combining receiver, transmitter and VLSI CMOS processing circuits on a single chip. This would not only significantly reduce volume and weight but could also reap cost benefits from volume production. Ma and the Wisconsin Alumni Research Foundation recently filed a patent for "A heat transfer-balanced solid-state high-frequency microwave high-power device structure."

Increasing demands on mobile communications are expected to drive future wireless operation frequency to the X-band (8-12GHz) and beyond, a broad frequency range populated by anti-collision radar, wideband satellite communication and space exploration, etc. But until recently, SiGe-based microwave power HBTs have been limited to L and C band operations. The overall power performance of SiGe-based HBTs are far from meeting all the requirements of future mobile communications. But with a well-designed device layout structure and considerations for parasitics, Ma's device demonstrates benchmark operation in terms of power amplification frequencies, output power and efficiency, overcoming the power amplification obstacles presented by the Si-based material.

New processor design seeks high speed at low power

Surpassing a system clock frequency of three gigahertz brought incredible processing speed and capabilities to desktop computer systems, but it also pushed peak power consumption for high-end microprocessors close to 100 watts. Assistant Professor Charlie Chung-Ping Chen is developing architecture and circuit technology that could dramatically reduce power consumption while maintaining high performance.

With dynamically reconfigurable parallelism (DRP), a microprocessor switches between high-performance and low-power modes according to real-time performance and power requirements. When combined with circuit techniques such as dynamic voltage and clock frequency adjustment, DRP could reduce energy use by as much as 60 to 70 percent.

To obtain better performance, circuit designers use selection mechanisms in traditional parallelism to select the right result among all possible scenarios when crucial information is ready. For example, with carry-select adders, two sums are simultaneously calculated at the same time as the carry is propagating. The final result is selected from those two sums whenever the carry is ready. By making the parallelism dynamically parallel, Chen's team will disable some levels of parallelism whenever the performance is not a critical factor. In the above example of a carry-select adder, those sum calculation modules are dynamically configured to make the whole adder either in carry-select mode or in carry-look-ahead mode. In this way, the whole carry-select parallelism is disabled.

Chen is also working on applying the idea on the architecture level. High-speed architecture features, such as branch prediction and superscalar, also can be dynamically reconfigured into power-saving mode if no heavy computation is involved. In addition, the sequencer, cache and register files can be partially turned off by putting some transistors in a sleep mode. The design challenge is not only in designing a reconfigurable module but in detecting the best configuration as well.

 





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Date last modified: 03-Oct-2003
Date created: 03-Oct-2003