David A. Wood Professor Address/E-mail Program Affiliations Education Fields of Interest Summary >>> Extended Homepage <<<

Contact Information

6369 Computer Sciences And Statistics 1210 West Dayton Street Madison, WI 53706

Tel: 608/263-7463 E-mail: david@cs.wisc.edu

Program Affiliations

• Electrical and Computer Engineering
• Computer Sciences

Education

• Ph.D. University of California, Berkeley, 1990
• B.S. University of California, Berkeley, 1981

Fields of Interests

• computer architecture
• performance evaluation
• VLSI systems design
• parallel processing
• computer memory system design

Summary

My main research goals lie in developing cost-effective computer architectures that take advantage of rapidly changing technologies. My research program has two major thrusts:

• evaluating the performance, feasibility, and correctness of new architectures, and
• developing new tools and techniques to facilitate this evaluation.

Currently, this research focusses on the following three areas:

• multi-paradigm multiprocessors, which efficiently integrate shared-memory, message-passing, and hybrid programming paradigms,
• a virtual prototyping system, which exploits the similarites of an existing parallel machine to simulate a hypothetical parallel machine,
• and, techniques for understanding and tuning program performance.

Recent results include developing a new interface---called Tempest---between user-level protocol handlers and system-supplied mechanisms. Tempest provides the mechanisms that allow programmers, compilers, and program libraries to implement and use message passing, transparent shared memory, and hybrid combinations of the two. Tempest mechanisms are low-overhead messages, bulk data transfer, virtual memory management, and fine-grain access control. The most novel mechanism---fine-grain access control---allows user software to tag blocks (e.g., 32 bytes) as read-write, read-only, or invalid, so the local memory can be used to transparently cache remote data.

We are exploring alternative ways to support this interface. The first---called Typhoon---is a proposed hardware platform that implements the Tempest mechanisms with a fully-programmable, user-level processor in the network interface. A reverse-translation table (RTLB) invokes the network processor when it detects a fine-grain access fault. We have simulated Typhoon on the Wisconsin Wind Tunnel and found that a transparent shared-memory protocol running on Typhoon performs comparably +/- 30% to an all-hardware Dir{N}NB cache-coherence protocol for five shared-memory programs.

We have also developed a new memory system simulation method that optimizes the common case---cache hits---significantly reducing simulation time. Fast-Cache tightly integrates reference generation and simulation by providing the abstraction of tagged memory blocks: each reference invokes a user-specified function depending upon the reference type and memory block state. The simulator controls how references are processed by manipulating memory block states, specifying a special NULL function for no action cases. Fast-Cache implements this abstraction by using binary-rewriting to perform a table lookup before each memory reference. On a SPARCStation 10, Fast-Cache simulation times are two to three times faster than a conventional trace-driven simulator that calls a procedure on each memory reference; simulation times are only three to six times slower than the original, un-instrumented program. We are also investigating using Fast-Cache's binary rewriting techniques to support the Tempest interface on existing hardware platforms.

Copyright 2005 The Board of Regents of the University of Wisconsin System Date last modified: Wednesday, 13-Dec-2000 10:59:48 CST Content by: david@cs.wisc.edu UW-Madison : COE : ECE : ECE Site Map UPDATE PROFILE