Our research group is investigating future processors and systems that provide high performance, power efficiency and high reliability. This research  is centered around a re-definition of architectural layering through Co-Designed Virtual Machines (VMs).  These VMs contain a layer of implementation dependent software that is developed concurrently  with the hardware. The VM software layer resides in a section of physical main memory  that is hidden from all conventional software. 

Current Students

• Nidhi Aggarwal
• Wooseok Chang
• Kyle Nesbit

PhD Grads

• Ramon Canal    PhD '03  (UPC-Barcelona)
• Jason Cantin    PhD’06
• Ashutosh Dhodapkar    PhD '04 
• Timothy Heil    PhD '02
• Craig Holt   PhD '79
• Shiliang Hu  PhD’06
• Quinn Jacobson    PhD '99
• Tejas Karkhanis PhD'06
• Ho-Seop Kim    PhD '04
• Steve Kunkel     PhD '87
• Eric Rotenberg     PhD '99 
• S. Subramanya Sastry    PhD '03 
• Yiannakis Sazeides    PhD '99
• Subbarao Palacharla   PhD '98 
• Shlomo Weiss PhD '82

Faculty Collaborators

• Mikko Lipasti

Selected Talks

Future Superscalar Processors Based on Instruction Compounding, Stamatis Vassiliadis Memorial Symposium, Delft, Netherlands, Sept. 28, 2007.

Virtual Machines: Supporting Changing Technology and New Applications, ECE Dept. Georgia Tech., November 14, 2006.

A Mechanistic Model for Superscalar Processors, IBM T. J. Watson Research Center, November 1, 2006.

Modeling Superscalar Processors via Statistical Simulation , Workshop on Performance Analysis and Its Impact on Design, Barcelona, June 28, 1998.

The Best Way to Achieve Vector-Like Performance? , 1994 International Symposium on Computer Architecture, Chicago, IL, April 1994.

SPECmarks Considered Harmful , slides prepared for panel on benchmarking, 1994 International Symposium on Computer Architecture, Chicago, Illinois, April 1994.

What the Means Mean: Benchmarking and Experimental Computer Architecture

Selected Papers

Configurable Isolation: Building High Availability Systems with Commodity Multi-Core Processors,   N. Aggarwal, P. Ranganathan, N. P. Jouppi, and J. E. Smith, 34^th Int. Symposium on Computer Architecture, June 2007.

Virtual Private Caches, K. Nesbit, J. Laudon, and J. E. Smith, 34^th Int. Symposium on Computer Architecture,  June 2007.

Automated Design of Application-Specific Superscalar Processors, T. Karkhanis and J. E. Smith, 34^th Int. Symposium on Computer Architecture, June 2007.

Fair Queueing Memory Systems, K. Nesbit,  N. Aggarwal, J. Laudon, and J. E. Smith, 39^th Symp. on Microarchitecture, Dec. 2006.

Stealth Prefetching, J. Cantin, M. Lipasti, and J. E. Smith,  12^th Int. Conf. on Arch. Support for Programming Languages and Operating  Systems, Oct. 2006.

A Performance Counter Architecture for Computing Accurate CPI Components,  S. Eyerman, L. Eeckhout, T. Karkhanis and J. E. Smith, 12^th Int. Conf. on Arch. Support for Programming Languages and Operating  Systems, Oct. 2006.

Reducing Startup Time in Co-designed Virtual Machines, S. Hu, J. E. Smith,  33rd Int. Symp. on Computer Architecture, pp. 277-288, June 2006.

Characterizing the Branch Misprediction Penalty, S. Eyerman, L. Eeckhout, J. E. Smith,  IEEE Int. Symp. on Performance Analysis of Systems and Software, pp. 48-58, March 2006.

An Approach for Implementing Efficient Superscalar CISC Processors, S. Hu, I. Kim, M. H. Lipasti, J. E. Smith,  12th Int. Symp. on High Performance Computer Architecture, February 2006.

Coarse-Grain Coherence Tracking in  Shared Memory Multiprocessors, J. F. Cantin, A. Moshovos, M. H. Lipasti, J. E. Smith, and B. Falsafi, IEEE Micro, pp. 70-79, Jan/Feb 2006.

The Architecture of Virtual Machines, J. E. Smith and R. Nair,  IEEE Computer, pp. 32-38, May 2005.
 
Prefetching Using a Global History Buffer, K. Nesbit and J. E. Smith,  IEEE Micro, pp. 90-97, Jan./Feb. 2005.

AC/DC: An Adaptive Data Cache Prefetcher,  K. J. Nesbit, A. S. Dhodapkar, and J. E. Smith,  International Conference on Parallel Architectures and Compilation Techniques, pp. 135-145, Oct. 2004.

A First-Order Superscalar Processor Model, T. Karkhanis and J. E. Smith, 31st Int. Symposium on Computer Architecture, pp. 338-349, June 2004.

Using Dynamic Binary Translation to Fuse Dependent Instructions,  S. Hu and J. E. Smith, 2nd Intl. Symp. on Code Generation and Optimization, March 2004.

Data Cache Prefetching Using a Global Address History Buffer,   Kyle J. Nesbit and J. E. Smith, Tenth Int. Symp. on High Performance Computer Architecture, February 2004.

Hardware Support for Control Transfers in Code Caches, H-S. Kim and J. E. Smith, 36th Int. Symp. on Microarchitecture, pp.253-264, Dec. 2003.

Comparing Program Phase Detection Techniques, Ashutosh S. Dhodapkar, J. E. Smith, 36th Int. Symp. on Microarchitecture, pp. 217-227, Dec. 2003.

The Complexity of Verifying Memory Coherence, J. F. Cantin, M. H. Lipasti, and J. E. Smith, Symposium on Parallelism in Algorithms and Architectures, June 2003.

Saving Energy with Just In Time Instruction Delivery, T. Karkhanis, P. Bose, and J. E. Smith, 2002 International Symposium on Low Power Electronics and Design, Aug. 2002.

An Instruction Set and Microarchitecture for Instruction Level Distributed Processing, H.-S. Kim, J. E. Smith, 29th Int. Symposium on Computer Architecture, May 2002.

Managing Multi-Configuration Hardware via Dynamic Working Set Analysis, A. Dhodapkar, J. E. Smith, 29th Int. Symposium on Computer Architecture, May 2002.

Statistical Simulation of Symmetric Multiprocessor Systems, S. Nussbaum, J. E. Smith, 35th Annual Simulation Symposium, April 2002.

Dynamic Microarchitecture Adaptation via Co-Designed Virtual Machines, A. Dhodapkar, J. E. Smith, International Solid State Circuits Conference, Feb. 2002.

Modeling Superscalar Processors via Statistical Simulation, S. Nussbaum, J. E. Smith,PACT '01, International Conference on Parallel Architectures and  Compilation Techniques, Barcelona, Sept. 2001.

Rapid Profiling via Stratified Sampling, S. Sastry, R. Bodik, J. E. Smith, 28th Int. Symposium on Computer Architecture, pp. 278-289, June 2001.

Saving and Restoring Implementation Contexts with co-Designed Virtual Machines, A. Dhodapkar, J. E. Smith, Workshop on Complexity Effective Design, Gothenburg, Sweden, June 30, 2001.

Relational Profiling: Enabling Thread-Level Parallelism in Virtual Machines, Timothy Heil and J. E. Smith, 33rd Int. Symp. on Microarchitecture pp. 281-290, Dec. 2000.

Very Low Power Pipelines using Significance Compression, R. Canal, A. Gonzalez, and J. E. Smith, 33rd Int. Symp. on Microarchitecture, pp. 181-190, Dec. 2000.

Trace Preconstruction, Quinn Jacobson and James E. Smith,  Proceedings of the 27th Annual International Symposium on Computer Architecture, June 2000 .

Vector Instruction Set Support for Conditional Operations, James E. Smith, Greg Faanes, Rabin Sugumar, Proceedings of the 27th Annual International Symposium on Computer Architecture, June 2000 ..

Improving Branch Predictors by Correlating on Data Values, Timothy Heil, Zak Smith, J. E. Smith, 32nd Int. Symp. on Microarchitecture, Nov. 1999.

A Study of Control Independence in Superscalar Processors, Eric Rotenberg, Quinn Jacobson, and James E. Smith, Proceedings of the 5th Annual International Symposium on High Performance Computer Architecture, January 1999.

Instruction Pre-Processing in Trace Processors, Q. Jacobson, J. E. Smith, Fifth Int. Symp. on High Performance Computer Architecture, January 1999.

Vector Architectures, Past, Present, and Future, R. Espasa, M. Valero, and J. E. Smith,  1998 International Conference on Supercomputing, June 1998.

Modeling Program Predictability, Y. Sazeides and J. E. Smith, Proceedings of the 25th International Symposium on Computer Architecture, July 1998.
 
Trace Processors , Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, and J. E. Smith, 30th Int. Symp. on Microarchitecture, Dec. 1997

The Predictability of Data Values, Yiannakis Sazeides and J. E. Smith,  30th Int. Symp. on Microarchitecture, Dec. 1997.

Path-Based Next Trace Prediction, Quinn Jacobson, Eric Rotenberg, and J. E. Smith,  30th Int. Symp. on Microarchitecture, Dec. 1997.

Complexity-Effective Superscalar Processors , Subbarao Palacharla, Norman P. Jouppi, J. E. Smith, 24th Int. Symp. on Computer Architecture, June 1997.

Selective Dual Path Execution , Timothy Heil, J. E. Smith, ECE Tech Report, Nov. 1996.

Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching , Eric Rotenberg, Steve Bennett, J. E. Smith, 29 Annual International Symposium on Microarchitecture, Dec. 1996.

Assigning Confidence to Conditional Branch Predictions , Erik Jacobsen, Eric Rotenberg, J. E. Smith, 29th Annual International Symposium on Microarchitecture, Dec. 1996.