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Nam Sung Kim
Assistant Professor
| Home : Faculty and Instructional Staff : | |
| Nam Sung Kim |
| Nam Sung Kim Assistant Professor |
| 4615 Engineering Hall 1415 Engineering Drive Madison, WI 53706 |
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Tel: 608/890-2616 Fax: 608/262-1267 E-mail: n*s#k&i$m^3_at_wisc.edu[removespecialchacters] |
*** 2010 ***
40. [Conf.] A. Sinkar and N. Kim, "Analyzing and Minimizing Effects of Temperature Variation and BTI on Active Leakage Power of Power-Gated Circuits," IEEE/ACM Int. Symp. on Quality Electronics (ISQED), Mar 2010.
39. [Conf.] D. Oh, N. Kim, C. Chen, Y. Hu, "Compatibility Analysis of Thread Migration and DVFS in Multi-Core Processor," IEEE Int. Symp. on Quality Electronic Design (ISQED10), Mar 2010.
38. [Conf.] D. Oh, N. Kim, et al., "Runtime Temperature-Based Power Estimation for Optimizing Throughput of Thermal-Constrained Multi-Core Processors," IEEE/ACM Asia-South-Pacific Design Automation Conf. (ASP-DAC), Jan 2010.
37. [Conf.] J. Lee, S.-T. Zhou, and N. Kim, "Impact of Multiple ABB and AVS Domains on Throughput of Power and Thermal-Constrained Multi-Core Processors," IEEE/ACM Asia-South-Pacific Design Automation Conf. (ASP-DAC), Jan 2010.
*** 2009 ***
36. [Conf.] N. Kim, J. Seomun, A. Sinkar, J. Lee, K. Choi, T. Han, and Y. Shin, "Frequency and Yield and Optimizations in Power-Constrained Designs," IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), Aug 2009. Acceptance Rate of Papers:52/210 (24.8%)
35. [Conf.] J. Lee and N. Kim, "Optimizing Total Power of Many-Core Processor Considering Supply Voltage Scaling Limit and Process Variations," IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), Aug 2009. Acceptance Rate of Papers:52/210 (24.8%)
34. [Conf.] M. Anderson, A. Davoodi, A. Sinkar, J. Lee, and N. Kim, "Statistical Static Timing Analysis Considering Leakage Variability in Power-Gated Design," IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), Aug 2009. Acceptance Rate of Papers:52/210 (24.8%)
33. [Conf.] A. Sinkar and N. Kim, "Analyzing Potential Total Power Reduction with Adaptive Voltage Positioning Optimized for Multicore Processors," IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), Aug 2009. Acceptance Rate of Papers:52/210 (24.8%)
32. [Conf.] J. Lee and N. Kim, "Throughput Analysis and Optimization of Power- and Thermal- Constrained Multicore Processors," in Proc. IEEE 46th Design Automation Conf. (DAC), July 2009. Acceptance Rate of Papers:148/682 (22%)
31. [Journal] M. Khellah, N. Kim, et al., "Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays with Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits," IEEE Journal of Solid State Circuits (JSSC), Apr 2009.
30. [Jounal] K. Bowman, J. Tschanz, N. Kim, et al., "Energy-Efficient & Metastability-Immune Timing-Error Detection and Instruction Replay-Based Recovery Circuits for Dynamic Variation Tolerance," IEEE Journal of Solid State Circuits (JSSC), Jan 2009.
*** 2008 ***
29. [Journal] D. Khalil, M. Khellah, N. Kim, et al., "Accurate Estimation of SRAM Dynamic Stability," IEEE Transactions on VLSI, Vol 16, No 12, Dec. 2008.
28. [Journal] D. Roberts, N. Kim, and T. Mudge, "On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology," Microprocessors and Microsystems, Aug 2008.
27. M. Khellah, N. Kim, et al., "PVT-Variations and Supply-Noise Tolerant 45nm Dense Cache Arrays with Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits," in Proc. IEEE VLSI Circuit Symposium, Jun 2008.
26. K. Bowman, J. Tschanz, N. Kim, et al., "Energy-Efficient & Metastability-Immune Timing-Error Detection and Instruction Replay-Based Recovery Circuits for Dynamic Variation Tolerance, Proc. IEEE Int. Symp. on Solid Circuit Conf. (ISSCC), Feb 2008.
*** 2007 ***
25. D. Khalil, M. Khellah, N. Kim, et al., "SRAM Dynamic Stability Estimation Using MPFP," Proc. 17th Int. Conf. on Microelectronics (ICM), Dec. 2007.
24. G. Chen, D. Blaauw, T. Mudge, D. Sylvester, and N. Kim, "Yield-Driven Near-Threshold SRAM Design," Proc. IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), Nov. 2007.
23. D. Roberts, N. Kim and T. Mudge, "On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology," Proc. 10th EuroMicro Conference on Digital System Design (DSD), August 2007.
22. J. Tschanz, N. Kim, et al., "Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging," Proc. IEEE Int. Symp. on Solid Circuit Conf. (ISSCC), Feb 2007.
21. M. Khellah, D. Somasekhar, Y. Ye, N. Kim, et al., "A 4.2Ghz, 130Mb/cm2, dual-Vcc SRAM in 65nm CMOS featuring active power management with autonomous compensation of PVT variation & aging impacts," IEEE Journal of Solid State Circuits (JSSC), Vol. 42, No. 1, Jan. 2007.
*** 2006 ***
20. M. Khellah, N. Kim, et al., "Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs," Proc. IEEE VLSI Circuit Symposium, Jun. 2006.
19. M. Khellah, N. Kim, et al., "A 4.2Ghz, 130Mb/cm2, dual-Vcc SRAM in 65nm CMOS featuring active power management with autonomous compensation of PVT variation & aging impacts," Proc. IEEE Int. Symp. on Solid Circuit Conf. (ISSCC), Feb. 2006.
*** 2005 ***
18. N. Kim, V. De, and T. Mudge, "Optimizing Total Power through Pipelining and Parallel Processing under the Presence of Process Variations," Proc. IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), Nov. 2005.
17. N. Kim, D. Blaauw, and T. Mudge, "Quantitative Analysis and Optimization Techniques for On-Chip Cache Leakage Power," IEEE Transactions on VLSI, Vol 13, No 10, Oct. 2005.
16. R. Bai, N. Kim, D. Sylvester, and T. Mudge, "Total Leakage Optimization Strategies for Multi-Level Caches," Proc. IEEE/ACM Great Lake VLSI Symposium (GLVLSI), Apr. 2005.
15. R. Bai, N. Kim, D. Sylvester, and T. Mudge, "Power-Performance Trade-offs in Nanometer Scale Multi-Level Caches Considering Total Leakage Power," Proc. IEEE/ACM Design Automation and Test in Europe (DATE), Mar. 2005.
*** 2004 ***
14. D. Ernst, N. Kim, et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," IEEE MICRO, Vol. 24, No. 6, Dec. 2004 - Top pick of Year 2004.
13. N. Kim, V. Bertaco, T. Austin, and T. Mudge, "Microarchitectural Power Modeling Technique for Deep Sub-Micron Processors," Proc. IEEE/ACM Int. Symposium on Low Power Electronic Design (ISLPED), Aug. 2004.
12. N. Kim and T. Mudge, "Single-VDD and Single-VT Super-Drowsy Techniques for Low-Leakage High-Performance Instruction Caches," Proc. IEEE/ACM Int. Symposium on Low Power Electronic Design (ISLPED), Aug. 2004.
11. N. Kim, K. Flautner, D. Blaauw, and T. Mudge, "Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power," IEEE Transactions on VLSI, Vol 12, No 2, Feb. 2004.
*** 2003 ***
10. N. Kim, et al., "Leakage Current - Moore's Law Meets Static Power," IEEE Computer, Dec. 2003 - Cover Feature of Month.
9. D. Ernst, N. Kim, et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," Proc. IEEE/ACM Int. Symposium on Microarchitecture (MICRO), Dec. 2003 - Best Paper Award.
8. N. Kim, D. Blaauw, and T. Mudge, "Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches," Proc. IEEE.ACM Int. Conf. on Computer Aided Desgn (ICCAD), Nov. 2003.
7. N. Kim, T. Mudge, and R. Brown, "A 2.3Gb/s Fully Integrated and Synthesizable Rijndael Core," Proc. IEEE Custom Integrated Circuit Conference (CICC), Sep. 2003.
6. N. Kim and T. Mudge, "The Microarchitecture for a Low Power Register File," Proc. IEEE/ACM Int. Symposium on Low Power Electronic Design (ISLPED), Aug. 2003.
5. N. Kim and T. Mudge, "Reducing Register Ports using Delayed Write-Back Queue and Operand Pre-Fetch," Proc. ACM Int. Conf. on Supercomputing (ICS), June 2003.
*** 2002 ***
4. N. Kim, K. Flautner, D. Blaauw, and T. Mudge, "Drowsy Instruction Caches - Reducing Leakage Power using Dynamic Voltage Scaling and Cache Sub-bank Prediction," Proc. IEEE/ACM 35th Int. Symp. on Microarchitecture (MICRO), Nov. 2002.
3. K. Flautner, N. Kim, S. Martin, D. Blaauw, and T. Mudge, "Drowsy Caches: Simple Techniques for Reducing Leakage Power," Proc. IEEE/ACM 29th Intl. Symposium on Computer Architecture (ISCA), May 2002.
2. N. Kim, T. Austin, and T. Mudge, "Low-Energy Data Cache Using Sign Compression and Cache Line Bisection," Proc. 2nd Annual Workshop on Memory Performance Issues (WMPI) in conjuction with 29th Int. Symposium on Computer Architecture, May 2002.
*** 1998 ***
1. N. Kim, H. Choi, S. Lee, S. Lee, I. Park, C. Kyung, "Virtual Chip: Making Functional Model Work on Real Target Systems," Proc. IEEE/ACM 35th Design Automation Conference (DAC), June 1998.
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