Hu, Yu Hen

Multimedia signal processing: fast algorithms, parallel VLSI architectures, and multi-processor synthesis methodology, artificial neural networks and fuzzy logic applications, computer-aided design, parallel processing

Publications

K. H. Yu, and Y. H. Hu, "Efficient scheduling and instruction selection for programmable digital signal processors," IEEE Trans. on Signal Processing, Vol. 42, No. 12, Dec. 1994, pp. 3549-3552.
D. J. Wang, and Y. H. Hu, "Multiprocessor implementation of real time DSP Algorithms", IEEE Trans. on VLSI Systems, Vol. 3, No. 3, Sept. 1995, pp. 393-403.
Hangu Yeo, and Y. H. Hu, "A novel modular systolic array architecture for full search block matching motion estimation", IEEE Trans. on Video Technology (Special issue on VLSI for Video Signal Processing), Vol. 5, No. 5, Oct. 1995, pp. 407-416.
Y. -T. Hwang, and Y. H. Hu, "A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays", J. of VLSI Signal Processing, vol. 11, No. 1&2, October/November 1995, pp. 133-150.
J. -M. Park, and Y. H. Hu, "On-Line Learning for Active Pattern Recognition", IEEE Signal Processing Letters, Nov. 1996, pp. 301-303.
S. Palreddy, Y. H. Hu, and W. J. Tompkins, "A patient adaptable ECG beat classifier using a mixture of experts approach", IEEE Trans. on BME, Vol. 44, No. 9, Sept. 1997, pp. 891-900.
Hangu Yeo and Y. H. Hu, "A high throughput modular architecture for three-step search block matching motion estimation", IEEE Trans. on Video Technology, vol. 8, No. 3, June 1998, pp. 299-315.
Y. H. Hu, "On the convergence of the CORDIC Adaptive Lattice Filter (CALF) algorithm", IEEE Trans. on Signal Processing, vol. 46, no. 7, July 1998, pp. 1861-1871.
Won-Ha Kim, T. Q. Nguyen, and Y. H. Hu, "Adaptive wavelet packet based image coding with optimal entropy-constrained Lattice Vector Quantizer (ECLVQ)", IEEE Trans. on Signal Processing, vol. 46, no. 7, July 1998, pp. 2019-2026.
Won-Ha Kim, Y. H. Hu, and T. Q. Nguyen, "Wavelet-based image coder with joint optimized Lattice Vector Quantizer and entropy coder", IEEE Trans. on Circuits and Systems, Part II, special issue on applications of Wavelet transformation, vol. 45, no. 8, Sept. 1998, pp. 1015- 1030.
Total 48 Journal articles and more than 120 conference papers

Selected Awards, Honors and Societies

Fellow, Institute of Electrical, Electronics Engineers (IEEE)
Secretary (1996-8), IEEE Signal Processing Society.
Board of Governors, IEEE neural network council (1996-7) representatives for Signal processing society.

Summary

My research interests focus on the design and implementation of high-performance signal rocessing algorithms as well as special purpose architectures to solve a multitude of engineering problems. Some projects studied nclude:

scheduling and assignment of recurrent DSP algorithms to multi-processor systems
optimal code generation for programmable DSP
Micro-architecture and design methodology for video signal processing
Low bit rate image and video coding and post-processing algorithms.
CORDIC based VLSI architecture for adaptive signal processing

I also have considerable interests in theory and applications of artificial neural networks and fuzzy systems to ECG signal processing.

Copyright 2009 The Board of Regents of the University of Wisconsin System
Date last modified: 17-Jul-2009
Content by: hu@engr.wisc.edu
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